Physical limitations of Complementary Metal-Oxide-Semiconductors (CMOS) technology at nanoscale and high cost of lithography have provided the platform for creating Quantum-dot Cellular Automata (QCA)- based hardware. The QCA is a new technology that promises smaller, cheaper and faster electronic circuits, and has been regarded as an effective solution for scalability problems in CMOS technology. Therefore, it is possible to generalize QCA to all digital components. Multipliers are considered as one of the most important building blocks of computational circuits in digital processing systems. The traditional design of Multipliers results in wasting the resources and increasing computational time. This paper presents an effective implementation of QCA Parallel Multiplier based on Wallace tree. It is able to significantly reduce the occupied area by reducing the number of QCA cells and therefore increases the speed of multiplying operation. The proposed QCA Multiplier is simulated by QCADesigner2.0.3 software. The simulation results confirm that the proposed QCA Multiplier works well and can be used in high performance circuits in QCA technology. Moreover, the proposed QCA Multiplier has less complexity and occupied area compared to other QCA Multiplier designs.

Electrostatic accelerators use a constant potential difference to create a suitable electric field and accelerate ions and electrons. One of the most widely used electronic accelerators in the industry, the dynamitron accelerator uses a voltage Multiplier circuit to generate the voltage required for acceleration. The capacitor elements of the voltage Multiplier circuit in the dynamitron accelerator are constituted of semi-cylindrical electrodes located in a columnar array. The design of this column of electrodes, also known as the voltage Multiplier column, is a complex process. It requires the study and simulation of electromagnetic fields and circuit models. The conceptual design of this structure is also complicated due to parameter interdependence. In this article, after a brief introduction to different parts of the dynamitron accelerator and details of voltage Multiplier columns, a process for the conceptual design of the voltage columns of a dynamitron accelerator is presented.

In this paper, the structure of a 16-by-16 unsigned hybrid (serial-Parallel) Multiplier has been proposed. Parallel Multipliers, in comparison with serial Multipliers, have higher speed and higher power consumption. In hybrid structures, to reduce power and increase speed, both serial and Parallel techniques are used. The proposed structure improves propagation delay and reduces power consumption using pipeline and retime techniques. Simulation results show that it has 5. 7 ns propagation delay and 2. 65 mW power consumption. The figure of merit for energy consumption is 15. 2 PJ. The proposed Multiplier has been designed using 0. 18 μ m TSMC process at 1. 8 V supply and simulated using Cadence tools. The layout of the Multiplier occupies 52414 μ m 2.

Two main insulating gases of SF6 and N2/CO2 mixture are employed to increase voltage capability of electrostatic accelerators. SF6 offers more insulating capability, but environmental and technical disadvantages of SF6 makes usage of N2/CO2 mixture a desirable option. This paper aims to replace SF6 with N2/CO2 in design of a 500 kV/30 mA Parallel-fed voltage Multiplier. High-voltage section of the accelerator is a capacitive structure which in combination with rectifying elements, generates the accelerating high-voltage. The structure which is called Voltage Multiplier Capacitive Structure (VMCS) is designed and analyzed in this paper. The first structure is designed to employ SF6 as insulating gas (VMCS500). Then, the structure is modified to be capable of using N2/CO2 as insulating gas with lower breakdown voltage (VMCS500-m). The modified structure requires more complex mechanical manufacturing process, but offers the simplicity of using N2/CO2 mixture, the option of using the modified structure with superior SF6 gas, increasing the output voltage and beam energy. CST EM STUDIO was used for capacitance calculation and electric field analysis. LTSPICE was used for equivalent circuit analysis of the high voltage generating section.

This paper presents two efficient implementations of fast and pipelined bit-Parallel polynomial basis Multipliers over GF (2m) by irreducible pentanomials and trinomials. The architecture of the first Multiplier is based on a Parallel and independent computation of powers of the polynomial variable. The second structure only even powers of the polynomial variable are used. The Parallel computation provides regular and low-cost structure with low critical path delay. In addition, the pipelining technique is applied to the proposed structures to shorten the critical path and to perform the computation in two clock cycles. The implementations of the proposed methods over the binary extension fields GF (2163) and GF (2233) have been successfully verified and synthesized using Xilinx ISE 11 by Virtex-4, XC4VLX200 FPGA.

In this paper, we introduce the notion of Multiplier in BL-algebra and study relationships between Multipliers and some special mappings, likeness closure operators, homomorphisms and (ʘ, Ú)-derivations in BL-algebras. We introduce the concept of idempotent Multipliers in BL-algebra and weak congruence and obtain an interconnection between idempotent Multipliers and weak congruences. Also, we introduce the special Multiplier ap and study some properties. Finally, we show that if A is a boolean algebra, then the set of all Multipliers of A is a BL-algebra under some conditions.

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In this note we obtain a reverse version of the Haagerup Theorem. In particular, if $ A \in \mathbb{M}_{n}$ has a $ 2\times2- $ principal submatrix as $ \left[ \begin{array}{cc}1& \alpha \\\beta & 1\\\end{array}\right]$ with $ \beta \neq \bar{\alpha}, $ then $ \Vert S_{A} \Vert > 1$ where the operator $ S_{A}:\mathbb{M}_{n}\longrightarrow \mathbb{M}_{n} $ is defined by $S_{A}(B) := A \circ B $ where $ "\circ " $ stands for Schur product.

Input-outputtable is a suitable way to identify the key sectors of regional economy. Multiplier coefficients of demand and supply extracted from input-output table may be used to calculate the innovating sectors of demand and supply and consequentially their key sectors. Multiplier coefficients are classified as gross and net (innovated by Oosterhaven&Stelder, 2002). . This study attempts to calculate the gross and net Multiplier coefficients for the province of Markazi. The results show that for regional studies the gross Multiplier coefficients work better than the net Multiplier coefficients. The net Multiplier coefficients divide economic activities in two groups of supply or demand; therefore, they cannot be used to create regional key sectors in Iran. However, the gross Multiplier coefficients divide the regional economic activities into four groups and can be used to identify the key sectors in Iran.